Minimum Cut Linear Arrangement of p-q Dags for VLSI Layout of Adder Trees

Two algorithms for minimum cut linear arrangement of a class of graphs called p-q dags are proposed. A p-q dag represents the connection scheme of an adder tree, such as Wallace tree, and the VLSI layout problem of a bit slice of an adder tree is treated as the minimum cut linear arrangement problem of its corresponding p-q dag. One of the two algorithms is based on dynamic programming. It calculates an exact minimum solution within nO(1) time and space, where n is the size of a given graph. The other algorithm is an approximation algorithm which calculates a solution with O(logn) cutwidth. It requires O(n logn) time. key words: graph algorithm, minimum cut linear arrangement, VLSI layout, adder tree, multiplier